About

Not understanding the logic of most envelope generators out there, i decided to try and experiment on my own. Although a big fan of CMOS 40XX logic, i decided to see if it's possible to pull something off with as few ICs as possible, preferrably a single chip. And, what do you know - an ADSR envelope is possible on a single TL074 quad op amp chip plus some passives and four transistors! But there's a catch: this is a joint decay/relase ADSR, akin to 'contour' style envelopes on early east coast synthesizers, e.g. Moog systems. Although Moog ended up pioneering the ADSR we all know and love, a fair amount of designs - including the infamous Minimoog - ended up running an earlier and simpler 3-knob style. Which is to say: it's not like i'm being a lazy ass that did not figure how to make it a full ADSR; instead, i'm being old-school cool and stylish. After all, limitation is the ignitor of creativity!

In all seriousness, this is a plain simple design that uses very few parts and definitely delivers for the simplicity of the build. This is mostly meant to be a beginner-friendly design for people that are only getting into SDIY to compliment their low pass gates and 40106 VCOs with. But, in all honesty, this simple design may as well find it place on a mini synthvoice or something! Naturally, for its simplicity, this ADSR comes with a number of drawbacks. Firstly, the decay and release times have a joint control, meaning you cannot have, say, a long decay and a near-instant release. Alas! Also, this design has no voltage control over any of its parameters; very sad, but also when you're a SDIY beginner, you don't really need to VC every single thing - trust me.

The interface is really simple. Two jacks: gate input and envelope output, the latter fit with an indicator LED. Pass a gate to the left one - get a slope from the right one. Any signal treated above 1.1v or so is treated as an active gate, so this envelope can be set off by LFOs or even audio. Three knobs total: rise, fall and sustain. Rise is for attack, fall is for decay and release, and sustain is, well, the sustain level. I didn't like the prospect of a "DEC+REL" control, so rise and fall it is! As all time-related knobs, rise and fall get shorter as the knob is turned clockwise. I know this may be counterintuitive, but it's like that for the absolute majority of my modules.

Finally, two switches help moving this envelope between functional domains. The top one changes its shape from heavily exponential to near linear. Expo is most useful on VCAs or VCFs for its organic slope, but has a drawback of having the very last moments of its slide-down rather pronounced, as all expo envelopes do. The linear option produces much more sterile and lab-feel results, and so, invokes a different feel. It is also somewhat shorter in time. I found it particularily useful with percussive sounds. The lower switch changes the time range of the envelope: left for usual envelope range, middle for audio - this thing is a bad filter and suboctaver! - and right for extended, extra-long, ambient-tier envelopes.

Although not the most malleable and complete function generator out there, it packs enough bang for the parts and effort it takes to make one. The only simpler envelope is a slew limiter processing a gate, but this one adds a whole bunch of expression to the deal!

Schematic

If you think about it, an ADSR envelope really is just a gate source driving a slew limiter, which also has to go down to some arbitrary sustain level after reaching its peak. A full ADSR would have different fall speeds for the "peak to sustain" and "sustain to zero" (decay and release) sections, but for this oldskool feel envelope, they're set by the same knob, which simplifies the design a fair bit, reducing it to quite literally a textbook slew limiter and some logic circuitry driving it.

A slew limiter, a.k.a. lag processor, is a device that, when provided with an input voltage, glides its output to match the input. The glide speed is adjustable in most slew limiters you meet in synthesizers, often separately for upwards and downwards glide. I already made a simple dual slew limiter a fair while ago, and simply reused its design here. The slew limiter is implemented over IC1B/IC1C in this design, and is pretty much a direct copy of SFP19. The rise/fall variable resistors and the capacitors C1-C3 form an RC lowpass filter network. An on-off-on RANGE switch allows selecting its range: when in the middle, only the tiny C1 is in use, and the circuit could as well be an audio filter effect. Enabling either C2 or C3 expands the circuit's time range to the one you'd expect usual envelopes and LFOs to operate in. The only addition is R2, a tiny resistor that prevents a short-circuit from IC1B to IC1C that nullfies any of the capacitors' efforts; in retrospect, it could be made as big as 1K to potentially enhance the usability of the controls' far ends. Either way, if this circuit were to receive a logic high pulse (gate) to IC1B's non-inverting (+) input, it would produce an attack-release envelope, sustained as long as the pulse/gate is held high.

In addition to the output jack, an LED is in place to indicate the envelope. It is driven from IC1C through R3 and offset to +12v through R4. LEDs don't light up until a certain threshold voltage is crossed, so to better indicate the envelope, the LED is brought to near-on through R3. This does not offset the actual envelope output.

The first issue with using that slew limiter alone as an envelope is that it can be fed any signal, really. Meaning if one module outputs an 5v pulse, and another - 10v, the envelope's peak voltage will change accordingly. This is quite suboptimal, because one expects homogenous behaviour from an envelope generator regardless of what kind of signal provides timing. This means that a gate detector has to be put in place, that accepts even low gates and processes gates of any height (in volts) into the same gate. Such action is obtained with a comparator made out of IC1A, on the very left of the schematic. A voltage divider of R17/R18 sets up a voltage of about 1/11(V+), or about 1.1v on Eurorack 12v bipolar power supply, on IC1A's inverting input. In case voltage on IC1A's non-inverting input exceeds that threshold, its output will be nearly at positive supply rail voltage, otherwise it lays almost at negative supply rail voltage. The exact values are about +11v and -11v respectively on Eurorack power, so i will just assume they are so for the rest of this article.

If the signal on IC1A's + is about the same as -, the comparator may start jittering; this is countered with a hysteresis feedback loop of R6/R7. Do note that this is not a negative feedback loop seen in summators, filters, etc. A positive feedback loop keeps an op-amp in comparator mode, but reduces the chances of jitter. R9 pulls the comparator's input down to ground, so that if nothing is patched into the gate input jack, no envelope is ever produced.

Now, if this comparator's output was piped directly to the slew limiter, we would get a nice and steady attack-release envelope. But i promised you an ADSR, albeit with a single D/R control! So, what does an ADSR do differently?

• After the envelope reaches its peak, it immediately falls to a predetermined sustain level
• While the gate is sustained, the envelope sits at that sustain level, not at peak
• As gate is released, the envelope goes from sustain to zero

Which means that the envelope's peak has to be detected, and that detector has to somehow swap in a voltage set by the sustain knob to the slew limiter (IC1B) instead of the IC1A's direct output. This way, the moment the slope reaches its peak after starting off, it will glide down to the user-selected sustain level, and then to zero as the gate is released. This is done by a fun little combination of IC1D as a comparator and the transistor setup between IC1A gate input and ICB/C slew limiter. While IC1A detects no gate, it outputs -11v. Note how it drives R3 through R15, which is closed in such case. Then R11 pulls T1's base up, T1 is open, and IC1D's + to negative supply voltage. IC1D is a comparator, and its - is tied to ground, hence when no gate is provided to the circuit, T1/T3 drag IC1D's + way below -, thus, IC1D outputs -11v.

Once a gate is provided, IC1A opens T2. Positive voltage goes through T2, through D2, and to the slew limiter, thus kicking off the envelope's attack phase. Since now ICA1's output is at about 11v, T3 is open, tying T1's base to -Vsupply, no longer tying IC1D's + to -Vsupply. This enables IC1D as a comparator. The slew limiter's output goes to its + input through R1. R5 and the return trimmer adds some offset and considerable hysteresis to the comparator; in tandem and when tuned correctly, this comparator's output will go off when the envelope reaches its peak.

Once the slew limiter outputs a high enough voltage, IC1D detects the envelope's peak, and its output shifts from -11v to +11v. This opens T4, and shorts out D2's anode ('positive' side) to ground. This means that a high voltage produced by IC1A/T2 no longer goes to the slew limtier through D2. However, the peak detecting comparator IC1D's now-high output itslf also goes through R14 to the voltage divider of the sustain potentiometer. This allows arbitrarily attenuating the voltage coming from IC1D and sending it to the slew limiter through D3 instead of the now-shut-off IC1A/T2 high-voltage pulse: here's our sustain level! D2/D3/R10 form a diode OR, or a maximum voltage selector - so the moment a high voltage from IC1A is gone, the slew limiter happily glides down to a (potentially) lower, manually picked sustain voltage. R14 limits the sustain headroom a bit; without it, a sustain that's *higher* than the peak is possible, which is not exactly nice. If the sustain knob is full-counterclockwise, the sustain voltage is zero and the envelope becomes a simple attack-decay (not an attack-release).

Let's imagine the sustain knob is set to middle, and the gate at the gate in jack is held high. The envelope sits at some sustain voltage indefinitely. Once the gate is released, IC1A stops seeing a gate and shifts from +11v to -11v. This closes T3, which stop shorting T1's base to -Vsupply and opens it up, thus tying IC1D's + input to -Vsupply as well. This effectively ignores the whole hysteresis-offset-envelope combo that's going on on IC1D's +, slams it into a big negative volage, which crosses well below the threshold of 0v set by grounding IC1D's inverting input. IC1D goes low, the sustain voltage is gone, T4 stops shorting whatever IC1A/T2 produce - but the gate has been released, so they're not producing anything anymore! This means that the voltages are zero or less behind both D2 and D3; R10 kicks in and pulls the slew limiter input down, hence the envelope slides from sustain to zero. Cycle complete!

If a new gate is provided during the release phase, the envelope will retrigger - as now IC1A+T2 are not shorted off by T4, and nothing stops them from driving the slew limiter up again. This behaviour is expected from east-coast style envelope generators, in contrast to west-coast style function generators that rise and fall indefinitely of the gate's length.

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