About
Hardcore build alert: this thing is sort of hard. Not extreme stuff like the VC sampler, but requires some skill. Total novices - build something simpler first! Unexperienced builders can build parts of this module as separate modules to avoid overloading themselves.
Random Factory is an improved version of the Shift Core Generator - it incorporates it as its subpart, and does much more for the same rack space. This module specializes on generating random gates and voltages, but is as well capable of semirandom, patterning and cyclic operation, up to the 8-stepper we all know and love (although if you're in the market for 8-stepper designs, better go here). This design is a combomodule that is aimed to bring more liveliness and easy to get random/pseudorandom patterns into an otherwise sequencer-based system.
The top left block of the module is a noise source: it provides 'white enough' flat noise, as well as lowpass and highpass filtered versions of it. Lowpass and highpass filters are simple RC (resistor-capacitor) filter circuits with buffers following them, so - no resonance, and the rolloff is mild, but the cutoff frequencies of both filters are variable with respective knobs.
To the right of the noise block is the shift core generator, an altered version of the SFP12 Shift Core Generator. It is a digital 8-bit shift register, and it's driven by two inputs: data and clock. Flat noise is normalled to the data input for instant random, and clock is, well, for clocking the register with an external clock (or you can use the lowpass noise). Both data and clock input have threshold knobs and attenuated threshold CV inputs: this setting determines a voltage above which the respecitve input (data or clock) is treated as a logic 1, and below which as 0. Every time the clock goes high (flips from 0 to 1, LED indicates that by lighting up), the last bit of the shift register is thrown away, everyting else gets shifted (first to second, second to third, ...), and whatever state the data input was in - 0 or 1 - is written to the first bit of the register. This way, with noise normalled to data and threshold set to noon, each clock pulse has an equal chance of writing a 0 or a 1 to the register, randomizing its contents on the fly. Using more predictable data sources brings cyclic or patterning sequences.
Although the binary outputs of the register itself are not available as gates, they are used to produce the six stepped CV outputs and the three gate outputs. Two of the CV outs are 'gaussian' (given the data is flat noise and data threshold is at noon) - they take one of the 5 states - from 0v to about 11v, and the highest chance is it will take state 3, while the lowest chance is to get state 1 or 5. The other four CV outs are 'flat' - they have equal chance of getting any state, under the same data settings described above. One may take one of 16 states, other has 32 possible states, and the last two have 64. Although the CV outs use the same data bits for deriving the voltages, the combination and order (for flat outs, the order won't matter for gaussian outs) is different for each CV digital-to-analog converter, so when one CV out goes up, the other is not guaranteed to follow - may stay the same or go down. This means the six outputs are usually percieved as unrelated, allowing more complicated randomizing of the patch.
The gate outputs are going from light to heavy in complexity, and output 0v when off and ~12v when on. The first gate out is simply the last (7th, if we're counting from 0) bit of the register. Feeding it back to the data input when the register has some 0s and 1s in it already may cycle it in an 8-step loop. The next one is bits 5 and 6 XORed together - a more complex pattern emerges when it is fed back to the register. Finally, the third out is NOT(bit 7 XOR bit 4 XOR bit 0) - the longest and most complex pattern source. Usually though, these just get used to trigger some drums and envelopes.
Finally, at the bottom right corner is a classic, standard analog sample and hold submodule. The result of comparing the clock input to the clock threshold (indicated by the LED) is normalled to its clock input, and lowpass noise is normalled to its signal input, making for an instant analog random value stream happening synchronously to the shift register action. This, of course, can be overridden with external sampled signal and clock sources. Lowpass noise is handy as a source, as the more its filter is open, the more diverse the value range becomes - likewise, the more you close the filter, the more the s-&-h out converges around 0v.
Although this is a bit of a complex build, this thing sure delivers - it's a bit of a cheat code for making the system more lively and unpredictable, at a pretty low cost for such power.
Schematic
Although the schem looks menacing, it really isn't. The scaries part is probably the data lines - but if made with a bit of planning and hacky veroboard techniques, it takes no time to make and not a lot of space. But, i will get back to those later.
The module starts with a noise source at top left: a classic reverse-breakdown BJT setup as the noise source, followed by a non-inverting amplifier of IC3A with a trimpot for gain setting. If you have a scope - monitor the flat noise output and trim until you're happy with the amplitude/squished negative half proportion. This isn't the best noise source ever, but it works and sounds great: i traded off the waveform symmetry for better frequency responce when testing it out on the breadboard and selecting the resistors/capacitors. The flat noise copy, buffered by IC3B, is passed through an RC lowpass and highpass filter separately. Those are then buffered by IC3C/D and go to the respective lowpass and highpass noise out jacks.
Below the noise generator are the shift register logic inputs. IC5A/B are set up as comparators, comparing the data/clock in to their respecitve passively summed threshold knobs and attenuated threshold CVs. The threshold CV attenuator will act as a bit of a fine tune knob if you have no CV plugged in: to avoid that, use another quad op-amp and dual-inverting-sum the init and the cv, then put the summator output to the inverting terminals of IC5A/B; i, however, don't care, and am quite happy with this behaviour. R36/37 and R58/59 are for stability reasons, they add a slight hysteresis feature to the comparators, preventing them for unwanted bouncing when the threshold and the signal input are very close to each other voltage wise. Flat noise output from the noise gen is normalled to the data input jack for instant random.
In the middle of the schematic is the shift register and its data bus. The register chip is a usual CD4015 dual 4-bit shift register, chained for a single 8-bit one. Beware of the fakes/bad ones: i had terrible experience with a sketchy looking one, but the one with more 'officially' looking print worked fine. Post-comparator data is passed to the register through a 10K resistor in order to have the CMOS input protection network to work and not heat up. For some reason, this trick doesn't work for clocking both halves of the 4015 with the same op-amp output + 10K, so instead there's a simple transistor buffer/gate repeater there. Be sure to add a power decoupling 10n capacitor close to the CD4015. For veroboard builders, i suggest wiring the outputs of the 4015 so that they form an actial 8-bit data bus on 8 adjacent traces, in correct oder. This will make the next steps much easier. At the bottom of the data lines, i installed an 8-pin header for a possible expansion module in the future.
To the right of the data bus are the CV output generators. For gaussian CV outs, each is a dual-inverting mixer with 4 inputs taken from the bus. They all contribute the same to the mix, so the thing can take 5 states overall. The 22K feedback resistor could be replaced with a 20K trimpot if you want to tune the output to play semitones/octaves/fifths/??? when plugged to a 1v/o VCO. The flat random outputs are crude DACs, buffered using op-amps. The DACs could be R2Rs, but they take up a lot of space and use up a lot of parts, so i just found the resistor values that do for a fair enough 'staircase' of non-repeating states, and went with that. Unlike for the gaussian CV outs, the order of bits matters for these ones as much as the selection of bits, as the smallest summing resistor will have the bit contribute the most to the sum. For this reason, i tried shuffling and reordering things as much as possible here, so that the values seem unlinked. This is a creative thing, so you can select your own set and order.
Veroboard builders: if you did the data bus as i hinted, you can now simply solder in all the resistors to the needed bit outputs so that they poke upwards from the board with the unsoldered legs, and are HORIZONTALLY (across the traces, not along) adjacent to the other resistors of the same DAC. Now you can simply solder their upper, unsoldered parts together using a resistor leg, uninsulated wire, and such. Run an (insulated) wire from the connected sides of the resistors to the buffer input - and you're done.
Below the CV outs are the gate outs: these use the CD4070 (or 4030) quad XOR gate chip for the XOR operation. Bit 7 is output as is, bits 5 and 6 are XORed using one 4070 XOR gate, and bits 4 and 7 are XORed, then the result is XORed to bit 0, and finally that is XORed to a constant 1 (+12v directly to the input), essentially making the last XOR a logic NOT, or an inverter. Rled can be selected to taste for the gate ouputs: 4.7K works great for me.
Finally, at the bottom left corner is the analog sample and hold, which is very boring, as it uses a ready-made sample and hold chip called LF398. I had one, so i decided to just roll with it. IC5D compares the input to a set threshold to make sure it looks like a gating pulse (so the thing is sinewave-friendly), and then it's converted to a short triggering pulse by the resistor-capacitor-diode network. This pulse makes the LF398 sample whatever is on its input to its output, and hold it until the next trigger is generated. The only catch with this circuit is C14, which is a capacitor that holds the charge for the LF398. Usual ceramic caps won't work here - they will droop towards zero very quickly. Ideally, the cap should be polystyrene, but polypropylene caps worked fairly well for me (see photos). Otherwise - no cathes in this circuit!
This build is possible on just four TL074s, two CMOS logic chips, and one specialized sample-hold chip. For a relatively low part count, it sure packs a punch in terms of how much it does. The build got a bit hectic and crammy for me, so if you're not feeling like dancing with your soldering iron on tiny areas of the veroboard, consider making this module wider, use more veroboard than i did, or even make the noise source, the analog sample-hold and the shift core generator three separate full-size modules. Take your time with the build and don't rush: unlike a lot of other stuff, this took me a good week to build, tediously testing each section after moving on to the next one.
